|
||
|
*停權中*
加入日期: Nov 2006
文章: 3,946
|
引用:
K10的L1、L2時脈都和Cache同步，L3才是自己的時脈  |
||||||||
2008-05-21, 02:26 AM
#21
|
|
|
Senior Member
 
加入日期: Jul 2004 您的住址: 一個都是女人的地方...
文章: 1,222
|
引用:
我記得K10的設計是L1,L2跟CPU同步 L3則是跟HTT同步 如有記錯請鞭  |
|||
|
2008-05-21, 10:04 AM
#22
|
|
|
Basic Member
加入日期: May 2008
文章: 21
|
嗯 Phenom這樣子還是很難令人興奮阿..
|
|
2008-05-21, 02:22 PM
#23
|
|
|
Power Member
加入日期: Oct 2004
文章: 594
|
引用:
在第七頁 From the load and store buffers, memory operations proceed to access the cache hierarchy, which has been totally redone from top to bottom. As with the P4, both the caches and TLBs are dynamically shared between threads based upon observed behavior. Nehalem’s L1D cache has retained the same size and associativity (check) as the previous generation, but the latency increased from 3 to 4 cycles to accommodate timing constraints. As previously mentioned, each core can support more outstanding misses (up to 16) to take advantage of the extra memory bandwidth. 整篇英文太多了，就等對岸翻譯了。 CPU架構圖↓↓  |
||
|
2008-05-22, 07:45 PM
#24
|
|
|
Master Member
  
加入日期: May 2002 您的住址: 書堆中
文章: 2,387
|
Phenom X4 9950這顆CPU耗電量高達140W，會不會太誇張了
__________________
|
|
2008-06-25, 09:38 AM
#25
|
|
|
*停權中*
加入日期: Jan 2008
文章: 1,281
|
引用:
等製程轉為 45nm 後，功耗應該會往下降。 或等 AMD 把 65nm 玩熟了，功耗也會降低。不過近來 Intel 製程升級的速度似乎加快了，AMD 恐怕沒機會玩熟 65nm，就被迫要盡快進入更先進製程，否則虧損會加劇 |
|
|
2008-06-25, 10:43 AM
#26
|
|
|
Junior Member
加入日期: Jun 2002
文章: 713
|
引用:
這產品一點都不符合節能減碳. |
|
|
2008-06-25, 12:23 PM
#27
|
|
|
Elite Member
加入日期: Jul 2000 您的住址: R.O.C
文章: 5,636
|
引用:
http://www.amd.com/us-en/Processors...5e10272,00.html 大家好像都忘記AMD有Cool'n'Quiet    TDP 140W又不是一直140W在消耗...... |
|
|
2008-06-25, 05:45 PM
#28
|
|
|
Advance Member
加入日期: Sep 2006
文章: 388
|
引用:
跟intel比 還是比較耗電  |
|
|
2008-06-26, 02:13 AM
#29
|
|
