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§@ªÌteszd@2014-02-08, 11:46 PM #184
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¥Ø«e°£¤FAltera»PXilinx¡ATSMC 20nm»sµ{³Ì¨üÆf¥Øªº«È¤á·íÄÝApple¤F¡C
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§@ªÌweiter5494@2014-03-19, 02:16 PM #222
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Ä«ªG¤U¥b¦~±À¥Xªº·s´ÚiPhone¤ÎiPad©Ò±Ä¥Îªº20©`¦ÌA8À³¥Î³B²z¾¹¡A4¤ë¶}©l©Ô°ª¦b¥x¿n¹qªº§ë¤ù¶q¡A¥B¥x¿n¹q²Ä2©u¤Î²Ä3©u±N¿W¦YA8¥N¤u¤j³æ¡C¤T¬P¹q¤l¡A¦]20©`¦Ì»sµ{¨}²v¤´§C¥B²£¯à¤£¨¬¡A¼È®É¨ÃµL±µÀò¥N¤uq³æ¡C
- chinatimes@Apr 14'14
With the ramping of
20-nanometer, which just started in a second quarter, we will have
a very, very small volume shipment. We'll have
much more volume in the third and fourth quarter at any new nodes, starting
with low margin. So, we expect there will be some dilution to corporate level margin starting from second quarter. The magnitude of that, it will impact by 1% in the second quarter. It will be slightly bigger than 1%, will be a very low single-digit impact on our second half. For the whole year, we still expect to see a slightly higher SGM compared to last year.
A8³B²z¾¹TSMC¥»©u¤p¶q§ë¤J¡A±q²Ä¤T©u¶}©l©ñ¶q¥B§Q¼í¤£°ª¡C
As for System LSI, revenue declined from the previous quarter as mobile AP demand decreased under weak seasonality. For System LSI, Samsung expects high-end mobile AP demand will remain weak through the second quarter, but earnings are expected to improve during the second half of the year as Samsung plans to seek growth momentum with solid sales of high-density CIS, aka ISOCELL, as well as the launch of new 20-nanometer AP products.
Samsung¤U¥b¦~³oÓ20nm²£«~¡A¦³¥i¯à¬OGalaxy S5 Prime·f¸üªºÂù¥|®ÖExynos 5430¸òiPhone 6ªºApple A8¡A²Å¦XTSMC©ñ¶q®Éµ{¡C
¦A¬ÝQualcomm»PMediatek¡I«eªÌ64-bitºXÄ¥´¹¤ùS808»PS810Áö±Ä20nm»sµ{¡A¤W¥«ÂI«o¬O¦b¤µ¦~©³»P©ú¦~ªì¶¡¡A¦ÓMTK«h¬O¶ÈªíºA·|¦³20nm²£«~¦b¦~©³¤W¡A¨ãÅé²Ó¸`¤£©ú¡C
Nvidia has jettisoned their plans for a 20nm Maxwell by the end of the year and are instead taping out 28nm Maxwell chips by the end of this month to launch at the end of this year or early next year. It was believed that Nvidia wanted to hold out for 20nm with their mid and high end GPUs. Unfortunately, that plan doesn¡¦t seem to be working out for Nvidia as TSMC is still having issues with their 20nm process, forcing Nvidia to launch their high end GM204 and mid-range GM206 at the 28nm process node as well. Similarly, AMD recently confirmed it is not moving to 20nm across all product lines (including GPUs) this year, although AMD hasn¡¦t confirmed whether this is due to to lack of 20nm supply from TSMC or if AMD doesn¡¦t yet have a competitive new architecture to put on the 20nm process. Either way, despite TSMC¡¦s claims of having a solid 20nm manufacturing process along with 16nm FinFET soon to come, we simply haven¡¦t seen a single, mass produced 20nm TSMC chip on the market.
AMD¸ònVidia¬Ò½T»{¤µ¦~²£«~¤´Ä~Äò¨Ï¥Î28nm¥´³y¡C´«¨¥¤§¡A´N¾aApple¼µ°_20nm¤@¤ù¤Ñ¤F¡C
Our 28 nanometer high-k metal gate has three options, 28HP, 28HPM and 28HPC. And this year these 28 high-k metal gate technology will be about 85% of the overall 28 nanometer in terms of the wafer.
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§@ªÌweiter5494@2014-03-19, 02:16 PM #222
...ªk¤Ú«h»{¬°§Þ³N°ÝÃD¤wÀò¸Ñ¨M¡A¨}²v¨Ó¨ì¤¦¨¡C
¥x¿n20©`¦Ì¤w¦b1¤ë¤U¦¯¡B©ó«n¬ìªºFab 14¥¿¦¡§ë¤ù¶q²£¡A¦Ó§Y¨Ï¦b¤WÓ¤ë¥x¿n©ó20©`¦Ì¶q²£¤W¾D¹J¤F¨Ç³\°ÝÃD¡A¤£¹L ¸g¥Ñ¿ï¾Ü¥t¤@ºØ¤£¦Pªº¬ã¿i²G(slurry)¡A¥x¿n¤w¶¶§Q¸Ñ¨M¤F¦bCMP(¤Æ¾Ç¾÷±ñ¥©Z¤Æ)»sµ{ªº¬D¾Ô¡A¥x¿nªº20©`¦Ì»sµ{¨}²v¡A¤]¤@Á|´£¤É¦Ü50%¡C
- BNP Paribas@Mar 18'2014
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4¤ë¥÷TSMCªk»¡·|«e¤i¡Aªk¤H°é¶Ç¥X®ø®§¡ATSMCªº20nm¨}²v¤w¥Ñ2¤ëªº50¢H³v¨B´£¤É¡A¥§¡¨}²v¬ù55~60¢H¡A°ªÂI¬ð¯}60¢H¡A¤£¦ý¶W¶VÄ«ªGn¨Dªº45¢H¡A§ó»»»»»â¥ý¤T¬P20©`¦Ìªº35¢H~40¢H¡CÁö¦b¨}²v¦³©Ò´£¤É¡A¦b¤Æ¾Ç¾÷±ñ¥©Z¤Æ¡]CMP¡^»sµ{¤¤¡A¦]¿ï¾Ü¤F¤£¦Pªº¬ã¿i²G¡]Slurry¡^§÷®Æ¡A¾ÉPÅ禬¥dÃö¡A³o§÷®Æ°ÝÃDÁöµM¤£ª½±µ¼vÅT¨}²v¡A¦ý«o·|¼vÅT²£«~ªº¹q«Héw«×¤Î¨Ï¥Î¹Ø©R¡A¦b¹q«H´ú¸Õ³¡¤À®£Ãø¹LÃö¡A¼vÅT¥X³f¡C¦¹»¡ªk¾DTSMC©x¤è»é¥¸¬°ÄA˶¥աAµL½]¤§½Í¡A¦]¬°¨}²v¬ð¯}ÃöÁä©TµM¦bslurry¡A¦ý¤£¨}ì®Æ¦³QÅç°h¦Ó¥¼§ë²£¡C
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§@ªÌweiter5494@2014-02-10, 03:47 PM #193
...16FF²£«~¤µ¦~¬Ý±o¨ì¡H
When the first 16nm FinFET ARM implementations will hit the market¡H We¡¦re squinting at this year.
- Pete Hutton, EVP and president of ARM¡¦s product group
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We have achieved
the risk production milestone of 16-FinFET in November 2013, November last year. And this month, we should pass the
1,000 hours so-called the technology qualification. So the technology is
ready for customer product tape-out. Our 16-FinFET yield improvement has been ahead of our plan. This is because we have been leveraging the yield learning of 20SoC. Currently 16-FinFET SRAM yield is already close to 20SoC. And with this status we are developing
an enhanced transistor version of 16-FinFET plus, with 15% performance improvement. It will be the highest performance technology among all available 16 and 14 nanometer technology in 2014. The above progress status is well ahead of Samsung.
- Mark Liu, President & Co-CEO of TSMC@4Q13 Earnings Call
¦b¦~ªìªk»¡·|¡]Jan 16¡^ÄÀ¥X16FF¤É¯Åª©ªº16FF+»sµ{ªº·¦V²y«á¡ATSMC¤W¤ëªk»¡·|¡]Apr 17¡^¶i¤@¨B´¦¶}¨Ó¦~¥ý¶i»sµ{¾Ô²¤¡C
We have a first 16FF product tapeout this month(Apr), it will ride on 16 FinFET process. 16 FinFET plus will be qualified in September. And for those customers taped out in the second half, I would say mostly, will be riding on the 16 FinFET plus. Majority of our process customers will run on 16 FinFET plus. And looking into the volume for the next year, I would say that most of the product will be run on 16 FinFET plus. The volume of 16 FinFET plus will happen in 2015. Even for some of the customer, initially their products sits on 16 FinFET, they also would like to migrate their second if market opened up indeed to upgrade their product. So I will see the vast majority will be 16 FinFET plus.
¥h¦~11¤ë§¹¦¨»sµ{»{ÃÒªº16FF¡A¤W¤ë¤w§¹¦¨º¥ó³]©u©w®×¡F¦Ó16FF+¹w©w¦b9¤ë¥÷§¹¦¨»sµ{»{ÃÒ¡A©ú¦~§ë¤J¶q²£¡C
ºîÆ[»sµ{ªu²¡A20SoC¡B16FF¡B16FF+¦@¥ÎBEOL¡A¬O¤@¯ß¬Û©Óªº¨t¦C»sµ{¡A¥Dn¬O¹q´¹Åé®t²§¡C±q20SoC¨ì16FF¬Oplanar¨ìFinFET¥~¥[·LÁY¡F16FF¨ì16FF+¬O¹q´¹Åé¯S©Êªº§ïµ½¡C¬Û§Î¤§¤U¡A20SoC¬O¹L´ç»sµ{¡A¦Ó16FF§ó¦hÄÝ©óÂú«¬»sµ{¡C
¦Ó¦U¾Õ¬ãµo¤Î¦æ¾Pªº¨â¤jÁp®uCEO¹ï16nm»sµ{ªº¸ÑŪ¡A«h±N¬OTSMC¥¼¨Ó¸gÀçÁZ®ÄªºÃöÁä¡C
The
tool commonality between 20 and 16 are 95%. So when the customer move from 20 SoC to 16 FinFET, we only need
to increase a very marginal amount of the capital to suffice that demand. The ASP and the product will be more competitive for our customer. So I'll
put it together as one node. But it does provide our customer their product grade or product spec to continually improve year-after-year.
- Mark Liu, President & Co-CEO of TSMC
20 SoC and 16 FinFET are
totally different device structure. Even the back-end design rule are similar, you cannot port one to the other easily. No, it won't be easy.
Porting from one foundry to the other foundry you are getting harder and harder. The real reason is all the device characteristic right now is related to the strain, all those kind of things, which you cannot just copy. You cannot de-layer or you cannot do the reverse engineering to look at it what is the device structure and get the same kind of IC characteristic. So, it's quite very hard -- actually very hard.
- C.C. Wei, President & Co-CEO of TSMC
The porting it happens and I just want to make two points.
We just have to live with it, deal with it. Let me point out two points. One is porting is cost more and more nowadays for this generation. I think it takes a lot of R&D resources to do that. Secondly, we just have to do better 16 technology. There are reasons to do that, because, first of all, we ramp 20 SoC massively this year and lot of learnings, a lot of process window control, a lot of design and collaboration with our customer, we will build ahead of our competitor. So we believe our 16 FinFET right on top of our 20 SoC, given they are
same design rule, will be more mature at the time compared with our competitor.
- Mark Liu, President & Co-CEO of TSMC
³o´[¡ASamsungªº¶i«×©O¡H¤W©u¤w§¹¦¨14 FinFET»sµ{»{ÃÒ¡A¦~©³§ë²£¡A©ú¦~¤W¥b¶}©l°^ÄmÀ禬¡C
As the company
completed qualification of 14-nanometer process during the first quarter, we plan to ramp up production of the
14-nanometer process which is expected to begin by the end of 2014 and
earnings contribution is expected from the first half of 2015.
PS¡GSamsung NAND°O¾ÐÅé»sµ{¤w¶i¤J§C©ó10~20nm¸`ÂI¡C
¤Þ¥Î:
§@ªÌweiter5494@2014-02-08, 10:41 PM #183
Âi±¤Wªº®ø®§Åã¥Ü¡A ...¦h¦~¥H¨Ó¡AIBM¤@ª½§êºtªº¬O§Þ³N¶}µoªº¨¤¦â¡]¯A¤Î°Ó·~¤Æªº¦Û¨²£«~³»¦h¬OPower³B²z¾¹¡^¡AÀqÀq¤ä¼µµÛCommon PlatformÁp·ù¹Ù¦ñªº°Ó·~¹B§@¡A¬OSamsung¸òGlofoªººë¯«¾É®v¡]¨ä¹êTSMC³Ìµh«ëªº¤HÀ³¸Ó¬OIBM¡^¡Afoundry»â°ìªºq³æ¦×·i¾Ô¤Ï¦Ó»P¨äµLÃö¡C
ªø´Á¨Ó¬Ý¡A¥X°â©Î¦X¸êªºµ²ªG©Î¦³¤£¦Pµ{«×ªº¼vÅT¡C¥X°âªº¸Ü¡AIBM²H¥X¥b¾ÉÅé»â°ì¡A´«¤H¾Þ½L¡A³ÌÃaªº¤U³õ¡ACommon PlatformÁp·ù¥i¯à¥Ë¸Ñ¡ATSMCÀò¯q³Ì¤j¡FÁa¨Ï¦X¸ê¡AIBMªº¼vÅT¤O¤]·|«d®z¡A¼vÅTÁp·ù¹B§@®Ä²v¡C·íµM¡AYSamsung»PGlofoY¤w¯à¿W·í¤@±¡A¦p¦¹½ÄÀ»¬Û¹ï¤p¡AÄ´¦p»¡¥þ²y¯à°Ñ»PASML EUV¥ú¨è¾÷§ë¸ê®×ªº¡ASamsung´N¬O¨ä¤¤¤@Ó¡C¥b¾É¤T°ê¹©¥ß¡A¥iµø¬°ÂùI¤@T¡]Intel¡BIBM¡BTSMC¡^°}À礧ª§¡C
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ÀsÀYÁI¦ì¡AIBMÁp·ù·s¥¬§½¯B²{¡C
¦P·½¦Û¬ü°ê¥»¤gªºIBM»PGlobalfoundries¦V¨Ó¤Í¦n¡A¹L±q¬Æ±K¡C¨âªÌ»P¯Ã¬ù¦{¥ß¤j¾ÇªºCollege of Nanoscale Science and Engineering²Õ¦¨ªº¬ãµoÅK¤T¨¤¤£¶È¼µ°_¯Ã¬ù¦{¥b¾ÉÅé²£·~¤@¤ù¤Ñ¡A¨ä¦ì©ó¹Ò¤ºEast Fishkillªº´¹¶ê¼t¡A¤]²o½u¤F¾Ô¤ÍGlobalfoundries¦b¹Ò¤ºªºMalta³]¥ßFab 8´¹¶ê¼t»P³y»ù2»õÁ⪺14nm¬ãµo¤¤¤ß¡A¥H«á8Ӥ뤺ÁÙ±N±a¨Ó100»õÁâ§ë¸ê»P±N°ª¬ì§Þ´N·~¾÷·|¦Û2200Ó¼W¥[¦Ü3000Ó¡A¦ÓIBM¹ê»Ú¤W¤]¬°¦¹´¹¶ê¼tªº¨}²v´£¤É¥I¥X«¤j°^Äm¡C¦bIBM¨M©w°h¥X´¹¶ê»s³y»â°ì¤§»Ú¡AGlobalfoundries¥ç¶¶²z¦¨³¹³Qµø¬°³Ì¦³§Æ±æªº¶R®a¡A°õ´x·í¦a¥b¾ÉÅé²£·~ªº¤jºX¡C
IBM also held talks with chip makers Intel and TSMC, but TSMC has dropped out of the talks after having studied the IBM chip plant and doesn't plan to add a new plant now in an overseas market. While Intel is still involved, Globalfoundries appears to have a stronger interest, they said.
- the Times Union
¦ÓSamsung±µ´ÎIBM¦¨¬°§Þ³N»âÀY¦Ï¡A±ÂÅv¤©GlobalfoundriesªºFab 8¡A¨Ï«nÁúªº¨â®y¡]µØ«°¡B¾¹¿³¡^»P¬ü°êªº¨â®y¡]Austin/Texas¡BMalta/New York¡^´¹¶ê¼t¦@¨É°ò©ó20nmªº14FinFET»sµ{¡A¦P¨B«Ý²£¡C
You
design once and then you can
go to either Globalfoundries or Samsung or both.
ų©óMade in USA´À¯Ã¬ù¦{©Ò±a¨Óªº°Ó¾÷»P´N·~¡]Samsung¥N¤uApple³B²z¾¹ªº¼w¦{´¹¶ê¼tS2¡A¦b2013¦~°^Äm30»õÁâÀ禬¡^¡A·í¦a´CÅéÅãµM¼ÖÆ[¦¹¤@µ¦²¤Áp·ù¡C¦¹¤@®a°ê±¡µ²¹ï±N¨ÓApple³B²z¾¹q³æ°Ê¦Vªº©Ò§Î¦¨ªºÅÜ¼Æ·í¤£®e©¿µø¡C
The potential to share manufacturing output could give the two companies a leg up because businesses such as Apple place a high priority on having the capacity to react to market demand. Samsung currently makes Apple's iPhone and iPad chips in Austin, but Apple, a major competitor with Samsung in the smartphone and mobile device market, has been looking to move some or all of its chip production to another company ouside the United States.
IBM¦bNanoCollegeªº¬ãµo¹Î¶¤±N«ùÄò¥[¤J10nm»sµ{¶}µopµe¡C
Both Samsung and Globalfoundries continue to work with IBM through a (research and development) presence in Albany as we explore technology options for 10 nanometers and beyond.
- Jason Gorss, GlobalFoundries spokesman.
³o´[TSMC¤S¬O¦p¦ó³W¹º10nm©O¡H
And for the 10 nanometer, we haven't announced it, but we did communicate with many of our customers that that will be the aggressive scaling of technology we're doing. And so, in the summary, our 10 FinFET technology will be qualified by the end of 2015. 10 FinFET transistor will be our third generation FinFET transistor. This technology will come with industry's leading performance and density.
- Mark Liu, President & Co-CEO of TSMC@4Q13 Earnings Call
10 FinFET will offer 2.2X of density improvement over its previous generation, 16 FinFET plus. So, currently, 10 FinFET development progress is well on track, but risk production will be in 4Q 2015.
- Mark Liu, President & Co-CEO of TSMC@1Q14 Earnings Call
14/16nmªºÃöÁä¡A3D¹q´¹Åé¤H¤H³Û°µ¡A°ÝÃD¬O¡A°£¤FIntel¥~¡A½Ö¿ì¨ì¤F¡H
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§@ªÌweiter5494@2014-04-28, 10:29 PM #256
...¥b¾ÉÅé³]³Æ°Ó¬ì½U¤W©u$8.32»õÀ禬»P$1.23ÁâEPS¬ÒÀu©ó¥«³õ¹w´Á¡A¦ý»F¦]´¹¶ê¼t¦b3D¹q´¹Åé»sµ{¨}²v°ÝÃDªº¥»©u®i±æ«o¥O¥«³õ¤Q¤À¥¢±æ¡C
Now in logic and foundry, with the introduction of the new 3-D gate architectures, the yield issues our customers are grappling with today are proving to be the most challenging that the industry have ever faced, and even the smallest variation and process margin can cause significant yield losses for these devices. Some of the issues of these processes people are dealing with are unique defect issues ¡K new etch steps that are all part of the FinFET process. That¡¦s just a small part of the complex technical challenge associated with bringing new 3-D device architectures to market...
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¦w°Õ¡ITSMC¥X«~¡A¥²ÄݨΧ@¡A±¾«OÃÒªº¡C
About the message that ASML¡]¦¹À³¬°´£°Ý¤§¤ÀªR®v¹ï¥t¤@³]³Æ°ÓKLA Tencorªº»~´Ó¡^saw
mobile FinFET delayed, I really don't know what it means. Talking about the FinFET technology difficulties, I must say our
16 FinFET technology development is well on track and our
new improvement is well on track and we are working with customers closely and we expect
to ramp up 2015. But I think one unique feature of our 16 FinFET is, our 16 FinFET has the
same design rule, back-end design rule like 20. So, we can leverage all the new learning, all the massive work in this year into next year 16 FinFET.
- Mark Liu, President & Co-CEO of TSMC
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§@ªÌweiter5494@2014-04-28, 10:29 PM #256
...¦Ó¾Ú·ç«H¤ÀªR¡A¹ï10nm»sµ{§ñÃö¦ÜnªºEUV¥ú·½¡Aìq°Ó¥Î®Éµ{¥Ø¼Ð¡]2017¦~¡^·|¦A«×¸õ²¼¡C»s³y°ÓASML¤W©uÀ禬£á14»õ¡AEPS¹F£á0.57¡F®i±æ¥»©u£á16»õ¡A§C©ó¥«³õ¹w´Áªº£á16.9»õ¡A¦P®É¥¼¥Xq³æ¶È£á10.7»õ¡A¤]¤j´T§C©ó¥«³õ¹w´Áªº£á16.4»õ¡C
The company is ¡§pushing out longer term targets¡¨ for its ¡§extreme ultra violet¡¨ lithography systems, and ¡§without the success of EUV, ASML has limited earnings growth potential.¡¨
- John Pitzer with Credit Suisse
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Ãö©óEUV¶i®i¿ð½wªº¨Æ¹ê¡ATSMC¤]¤£¤©§_»{¡C³o·N¨ýµÛ¦b16nm»sµ{«á¡A±µ¤U¨Ó¤´µL¥iÁ×§K°§C¦¨¥»ªºÃø«×¡C
Today,
EUV is not up to the production spec. Actually the most recent breakthrough was a 30 watt and now they have a higher 80 watt machine that we're still working toward that goal. So
EUV will not be inserted in 10 nanometer at the start, because it will slower the pass-through window. So our EUV team is still continuously working on EUV, hopefully to insert a few layers
after the 10 nanometer process start to qualify as a follow up process simplification. And that will meant to be
second half next year.
- Mark Liu, President & Co-CEO of TSMC
¶Â¨ò¦Y¹Lªe¡ATSMC²×©ó¶V½u¡A¤@¸}½ò¤J«Ê¸Ë·~¦a½L¡AASE¡BSPIL¦pÁ{¤j¼Ä¡ASiP¡BCoWoS¡]»PTSMC¼²m¡H¡^»ô¥X¡C¤£¹L¤ù»y°¦¦r¡ATSMC¤´ÅýÆ[²³¹ïInFO»PCoWoS¤´¼Z¤¨½Ãú¡C
The difference between the
InFO¡]Integrated Fan-Out¡^and the CoWoS is actually
the geometry to connect multi-dies together. In the CoWoS, actually we are using very small geometry, actually 65 nanometers of geometry to connect the multi-dies together. In InFO, we're using the larger geometry, which are still technical confidential information. But the cost is much, much lower. We will see inFO product out, but that will be our customer's schedule. Technology is close to be
in production ready probably early next year.
- C.C. Wei, President & Co-CEO of TSMC
¦p¦¹¯«¾¹¡A¥~¸ê©~µM°Û°I¡H
While the InFO or vertical stacking fan-out may be able to offer a lower cost and a simplified process flow to the chipset makers to replace the current PoP package, the technology is still at a very early stage and the risk of InFO remains way too high. The molding compound process may warp the wafer and induce an extremely high yield loss, which is likely to undermine the cost structure.
- Roland Shu of Pritchard
«D±M·~Æ[ÂI¡ATSMCÂǥѦV¤U¾ã¦Xªº2.5D«Ê¸Ë¥[ȼҦ¡¡A¨ÓÀ±¸É«È¤á¹ï28nm¥H«áªº¦yºÝ»sµ{¦¨¥»°´T¤£¨ÎªººÃ¼{¡A¨ä®t²§¤ÆªA°È¥H°Ï¹jÄv¼Äªº©T¼Î·m³æ°Ê¾÷¤Q¤À©ú½T¡CµMÆ[¹îCoWoSµo¥¬¹O¦~ªº¶i®i¡A¥[¥H¦¹¨è¦A±ÀInFO¡AÅãµM«È¤á¶R³æª¬ªp¤í¨Î¡A§V¤OªÅ¶¡¨ÌµM¡C¥u¬O¡A³o¯ë®vªk±ªO·~ªÌ¾ã¦XIJ±±¥\¯àªºµ¦²¤¡A¨s³º¬O¥[«ù¡A©Î¬O¾ð¼Ä¡H¦P®É¡A¹ï¤â¤w¹ê²{¥HTSV¦bDRAM§@¦P½è»r´¹°ïÅ|¡A¥¼¨ÓÁÚ¤J²§½è°ïÅ|¡A¬D¾ÔInFOªº¼ç¤O®£Ãø¥H§C¦ô¡CWait and See¡I
PS¡G
TSMC¤µ¦~28nm¥X³f¡]in terms of the wafer¡^¤¤¡A28HKMG¡]28HP¡B28HPM¡B28HPC¡^±N¥e¤ñ85%¡C
28HPm - ´£³t30% vs 28LP
20SoC - ´£³t20% vs 28HPm
16FF - ´£³t40% vs 20SoC
16FF+ - ´£³t15%¡B¸`¯à30% vs 16FF
16FF+ - ´£³t40% vs 20SoC