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Silent Member
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2013年初與Intel簽訂14nm FinFET代工訂單的TSMC老客戶Altera，由於Intel方面進展不如預期，近期回頭向台積電追加20nm產能。之前Xilinx已宣佈新一代架構Ultrascale的FPGA產品以TSMC的20nm導入量產。
- udn@2013/12/02
2014年4月中，Altera與TSMC共同宣布，前者的Arria 10產品線同時採用了TSMC的20SoC製程與細間距銅凸塊封裝技術，較前代28nm產品節能40%。TSMC宣稱其銅凸塊封裝良率可達99.8%。
2014年4月24日，Altera再宣布採用Intel的14nm製程的測試晶片已產出，未來Stratix 10產品將搭配所測試的功能IP。Stratix 10只要Stratix V的30%功耗即可達相同效能。相較之下，Stratix 10效能改善至1.4~1.6倍，甚至在1.3倍功耗下可達2倍效能，只要在新架構上進行部分修改。若只需求今日的效能水平，中階定位的Arria 10（TSMC 20SoC-based）即可滿足。
Testing vital elements of our FPGAs in 14nm Tri-Gate silicon allows us to validate device performance early in the design process and significantly accelerate the availability of our 14nm-based products.
- Brad Howe, senior vice president of research and development at Altera
1Q14 Xilinx財報顯示，$6.178億營收優於預期，0.53鎂EPS讓市場失望；展望本季營收持平到微增4%。其七成營收來自季增40%的28nm產品，20nm產品開始結果。
“Already bearing fruit” with chips at 20-nanometer measurements.
瑞信提高對Xilinx營收估值，反而降評。TSMC代工20nm晶片的出貨速度與中國4G基地台的部署進展會是兩大關鍵因素。
The company is up against some structural issues with its markets, including the pace at which manufacturing partners can actually manufacture the 20-nano parts, and also just how quickly the market for LTE wireless broadband will get built this year in China. Xilinx chips go into communications equipment sold to China Mobile and other carriers in the country, so any delay hits Xilinx as well.
1Q14 Altera財報顯示，受惠於中國積極的4G建設，$4.61億營收與0.37鎂EPS，皆優於預期；展望本季營收季增2%~6%。目前TSMC與Intel正分別與其合作20nm、14nm先進製程產品。
The quarter benefitted from “stronger than anticipated Chinese LTE deployments.” We are now shipping Arria 10 FPGAs that offer more logic capacity than any other 20 nm FPGA and speeds that exceed the prior generation high end. Simultaneously, we are making solid progress in the development of our Stratix 10 devices, which use Intel’s 14 nm Tri-gate process plus a new FPGA logic architecture to deliver performance twice that of our current high-end FPGA, with vastly more logic resources, lower power and cost.
除了已進入量產的20nm，TSMC正試產16FinFET，預計2015年初量產；而較20SoC提速40%、較16FinFET提速15%（或同速下節能30%）的進階版的16FinFET+製程，預計三季末完成客戶認證，年底可進入量產。至於第三代3D電晶體製程10FinFET則規劃在4Q15試產，2016年末至2017年初之間進入量產。
半導體設備商科磊上季$8.32億營收與$1.23鎂EPS皆優於市場預期，但肇因晶圓廠在3D電晶體製程良率問題的本季展望卻令市場十分失望。
Now in logic and foundry, with the introduction of the new 3-D gate architectures, the yield issues our customers are grappling with today are proving to be the most challenging that the industry have ever faced, and even the smallest variation and process margin can cause significant yield losses for these devices. Some of the issues of these processes people are dealing with are unique defect issues … new etch steps that are all part of the FinFET process. That’s just a small part of the complex technical challenge associated with bringing new 3-D device architectures to market Now, in memory the market leaders continue to demonstrate a commitment to pushing capex investment in both DRAM and NAND. However, they’re also facing similar challenges to logic when they deal with their leading edge complexity … There’s uncertainty over the timing of follow-on production for 3-D NAND … It’s clear from our discussions with customers that despite near-term slowdown in demand their intentions are continue to execute strategy for growth at the leading edge and invest at high level to achieve and advance their competitive roadmap. But it is also clear that issues related to leading edge device yield and high concentration of demand across a consolidated customer base and uncertainty over the timing of follow-on capacity have introduced a degree of variability into our quarterly demand forecast and have made visibility into our customer production plans extremely challenging today.
而據瑞信分析，對10nm製程攸關至要的EUV光源，原訂商用時程目標（2017年）會再度跳票。製造商ASML上季營收��14億，EPS達��0.57；展望本季��16億，低於市場預期的��16.9億，同時未出訂單僅��10.7億，也大幅低於市場預期的��16.4億。
The company is “pushing out longer term targets” for its “extreme ultra violet” lithography systems, and “without the success of EUV, ASML has limited earnings growth potential.”
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