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weiter5494
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加入日期: Nov 2013
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作者weiter5494@2013-12-02, 11:07 PM #31
We quantified Intel’s die size advantage over TSMC to be 35% on 14nm and 45% on 10nm. We expect this to translate into share gains in tablets and smartphones.
- Mark Lipacis with Jefferies & Co.



看貓仔無點?TSMC反擊Intel稍早前對其16FF製程的誤導。

We take the approach of significantly using the FinFET transistor to improve the transistor performance on top of the similar back-end technology of our 20-nanometer. This transistor performance and innovative layout methodology can improve the chip size by about 15%. This is because the driving of the transistor is much stronger so that you don't need such a big area to deliver the same driving circuitry. Our 16-FinFET scaling is much better than Intel's set but still a little bit behind. And the 10-nanometer, which we haven't announced, will be the aggressive scaling of technology we're doing. 10 FinFET transistor will be our third-generation FinFET transistor.
- Mark Liu, co-CEO of TSMC

從TSMC回應Intel以過時數據低估其16FF的微縮成效發言來看,Intel 14nm製程的die size優於TSMC 16FF約20%,而TSMC預定在採用第三代FF電晶體的10nm製程上與Intel並駕齊驅,而非有45%微縮面積的落差。TSMC預期16FF將如期於2015年首季量產。而之前業界推估其10nm製程將落在2017年,符合ASML量產級EUV光刻機的時程。




不過TSMC也毫不留情海K Intel:讓你技術領先又如何?

However, the real competition is between our customers' product and Intel's product or Samsung's product.

好奇的是,16FF是TSMC第一代FinFET電晶體技術,10nm會採用第三代技術,那第二代跑哪兒了?
舊 2014-02-05, 01:44 PM #168
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