Marvell近來諸事順利，LTE產品喜訊頻傳，還有私募基金KKR入股6.8%，量能皆備之餘，Intel向其頻頻招手。後者雖然不是TSMC前三大客戶之一，面子問題TSMC也要兢兢業業。

We believe that Intel is gaining customer traction in their foundry business, consistent with the company’s recent commentary to open their foundry services to additional customers. We believe Marvell is a potential good fit for Intel in integrated baseband/application processors. Our sense is that performance gains using Intel’s 22nm FinFet process would be substantial for Marvell, providing the catalyst for this relationship. Marvell would be a particularly suitable candidate given their strong relationship with Intel (they acquired Intel’s communications and applications processor business in 2006). Meanwhile, Marvell is enjoying some near-term momentum, having just qualified for VoLTE on AT&T and recently announcing wins at ZTE and Coolpad for TD-LTE baseband/AP, boding well for future volumes.
- Glen Yeung of Citigroup


20nm製程成本沒有更便宜，已是業界共識。EDA大廠明導曾指出，20nm製程將是首個無法降低晶片成本的製程。

At 20nm，the first node ever which will not deliver cheaper chips, there will be no cost/transistor cross-over for the first time in history. It’s very disturbing. Traditionally the cost per wafer increases 15/20% at each node. With FinFET, the cost increase is more like 40%. Added to that is the additional cost of double-patterning which comes in at 20nm.
- Wally Rhines, CEO of Mentor Graphics@IEF2013 in Dublin

而TSMC技術高層也明瞭28nm之後的成本上揚幅度驚人。

The prospective cost of a 10nm wafer appeared to be about 4x the cost of a 28nm wafer. We need many innovations to bring the cost down. The two most important innovations to achieve this are 450mm and EUV. Progress towards 250W source power EUV，which I expect to see it by 2015, must not slow down,
- 施奕強, senior director for R&D at TSMC@IEF2013 in Dublin

這是近年來業界紛紛疑慮Moore's law已至盡頭，微縮技術將窮，須加上先進封裝技術來持續提高整合度，維持成本優勢。某種程度上，這解釋了TSMC為何在數年前便決定跨界封裝領域，發展CoWoS！


Bulk Si材料特性不如SOI, 卻是成本低廉；當年大力挹注SOI技術者，如GloFo，反成了冤大頭。在戮力搶單TSMC的28nm客戶之餘，GloFo依然持續替STMicro代工28nm FD-SOI產品。稍早前STMicro成功展示了標準電壓下速度高達3GHz（極低電壓下亦可達1GHz）的Cortex-A9產品。

若以平面電晶體應用在Intel的22nm製程搭配FD-SOI，無須3D FinFET即可達成具競爭力的功耗效能，特別是還能沿用原先閘極先製的製程。據傳Intel擬簽約取得FD-SOI技術授權，來搭配14nm以下製程。





mobility更好的三五族元素也是個選項，IMEC發展藍圖已規劃至5nm，7nm時加入三五族元素，並已成功在10nm製程中以SiGe取代Si。

華爾街點名Intel在明年使用三五族元素製程在自家產品，不排除也透過此新製程進軍晶圓代工業。

Intel is expected to initiate chip production using III-V semiconductor circuits, potentially as early as 2015. The use of III-V compounds as channel materials (possibly on SOI substrates) create the potential for substantial power savings in addition to the benefit of extending a roadmap of future shrinks. While III-V makes the most sense for logic devices (e.g. Intel’s own microprocessors), we anticipate Intel will offer this process to prospective foundry customers as well […] Producing baseband/AP chips for Marvell indeed implies that Intel will be fabricating ARM solutions on their 22nm process.