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作者weiter5494
I don’t buy Altera’s claim that manufacturing costs to make ASICs will rise more sharply as chips get made at smaller and smaller feature sizes. It is not clear to us why the design costs rise with each more advanced semiconductor node to the extent that Altera claims.
- David Wong of Wells Fargo
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Cost of tool (Altera/Xilinx pretty much offer tools out for free to tier1/2 customers), cost of engineers (many FPGA designs don't even have a dedicated verification team, whereas ASIC design team consists of mostly verification engineers), cost of respin (revision A0 almost never works), cost of poor yield for new process, etc.
Wells Fargo needs to hire a new analyst if David Wong can't comprehend that.