Intel對自家技術的信心來自於Moore's Law - 被半導體業界多年來奉為圭臬，近期卻漸行漸遠的金科玉律，描繪微縮科技的演進，使單位面積的晶片內得以塞入越來越多的電晶體，換來造晶成本的降低或效能的提升。
TSMC自45/40啓動的half-node戰略以time-to-market之勢橫掃foundry領域，讓競爭對手（不含IDM業者Intel，其採取full-node策略）爭相模仿，盡皆聚焦於閘極（transistor）微縮，並沿用前代線幅（interconnect）微縮，以加速上市（foundry BEOL跟fabless設計工具可續用）。
TSMC 28nm - 28nm trans. + 40nm inter.
TSMC 20nm - 20nm trans. + 28nm inter.
TSMC 16nmFF - 16nm trans. + 20nm inter.
Rival 14nmFF - 14nm trans. + 20nm inter.
然而half-node戰略的取巧（或與現實妥協）與Moore's Law脫節，在28nm以後的製程已無法大幅縮小晶片面積，加以多重曝影成本跟EUV研發延宕，每晶片的價格下降趨勢因而停滯，僅獲得功耗跟效能上的改善。所以，期待以2.5D/3D封裝來提高IC整合度的業者與日俱增。
與foundry對手不同，Intel歷年來奉行full-node戰略，在閘極電晶體與內連線幅的微縮上皆同步演進，這是令其自豪的製程領先優勢。同時，在EUV技術與18吋晶圓設備于2016年就緒之際，Intel可能是唯一能同步整合的業者。
引用:
|
作者weiter5494
Most importantly, Intel appears to be extending its manufacturing lead over TSMC, which we think translates to share gains in tablets and smartphones. Intel was driving transistor cost down faster than it has before, while TSMC stalls on the transistor cost curve. We quantified Intel’s die size advantage over TSMC to be 35% on 14nm and 45% on 10nm. We expect this to translate into share gains in tablets and smartphones.
- Mark Lipacis with Jefferies & Co.
Intel believes it will have ~35% advantage in area scaling on 14nm FF (vs. 16nm TSMC) and 45% on 10nm (vs. TSMC). Intel has all of the tools to succeed, and those tools appear to be even better than ever in next 2–4 years.
- Doug Freedman at RBC Capital Markets
Intel believes that it currently has a 3.5 year advantage over TSMC and that it is currently driving cost down faster than Moore’s Law. Overall, we believe that Intel’s manufacturing edge could make a significant difference in the future competition with vendors that use TSMC and Samsung.
- Daniel Amir with Lazard Capital Markets
...
|
針對市場上對其14nm製程進度延遲一季的憂慮，Intel澄清6、7、8三個月間的良率大幅下滑造成Broadwell處理器延遲至1Q14, 然目前良率已逼近22nm產品水平。
