叫模擬我覺得怪怪的
SATA和PATA同屬於ATA規範...
向下相容這應該不意外..
而SAS將ATA納入本身的規範子集

剩下的是硬線設計的問題...

Intel在ICH Datasheet上的描述:
The SATA function in the ICH10 has three modes of operation to support different
operating system conditions. In the case of Native IDE enabled operating systems, the
ICH10 utilizes two controllers to enable all six ports of the bus. The first controller
(Device 31: Function 2) supports ports 0–3 and the second controller (Device 31:
Function 5) supports ports 4 and 5. When using a legacy operating system, only one
controller (Device 31: Function 2) is available that supports ports 0 - 3. In AHCI or
RAID mode, only one controller (Device 31: Function 2) is used enabling all six ports.

The MAP register, Section 15.1.29, provides the ability to share PCI functions. When
sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,
Function 1 (IDE controller) is hidden by software writing to the Function Disable
Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used.

The ICH10 SATA controllers feature six sets of interface signals (ports) that can be
independently enabled or disabled (they cannot be tri-stated or driven low). Each
interface is supported by an independent DMA controller.

The ICH10 SATA controllers interact with an attached mass storage device through a
register interface that is equivalent to that presented by a traditional IDE host adapter.
The host software follows existing standards and conventions when accessing the
register interface and follows standard command protocol conventions.