工藝技術細節:


http://www.amdzone.com/index.php/re...0-black-edition

The major change in Phenom II is that it is built using a 45nm immersion lithography manufacturing process which, "enables higher frequencies, tighter tolerances and lower current leakage." The other major change is the L3 cache which is now three times as large at 6MB over 2MB of Phenom and the L3 cache is also 2-cycles faster.



Major silicon enhancements for 45nm AMD Phenom II:

45nm immersion lithography manufacturing technology enables higher frequencies, tighter tolerances and lower current leakage
6MB L3 cache (up from 65nm Phenom's 2MB)
2-cycles faster than 65nm Phenom L3
Increased DRAM bandwidth
Cache flush on halt: Core's L1 and L2 flush into shared L3 after a core enters a halt state allowing the core to drop to a lower speed and save power
Path-based indirect branch prediction
2x increase in core probe bandwidth
Larger load/store buffering / larger floating point buffering / reduced MAB (missed buffer) lifetime
Improved LOCK pipelineing: (LOCK is an instruction prefix) this improves performance when multiple LOCKS are in process simultaneously
FP MOV compute optimization: Floating point register-to-register move instruction improvements



Fab location: Fab 36 wafer fabrication facilities in Dresden, Germany

Process Technology: 45-nanometer DSL SOI (silicon-on-insulator) technology
Approximate Transistor count: ~ 758 million (45nm)
Approximate Die Size: 258 mm2 (45nm)
Max Ambient Case Temp: 62o Celsius
Nominal Voltage: 0.875 - 1.5 Volts
Max TDP: 125 Watts
*NOTE: MC configurable for dual 64-bit channels for simultaneous read/writes


http://wqsky.com/hk/list/4642.htm
immersion lithography 濕浸式微影/沉浸式光刻

Fourth-generation Strained Silicon 第四代張力矽晶

Ultra-low-k Dielectrics 超低K電介質

High-k/metal Gates 高K柵介質和金屬柵電極



PS:據說 High-k材料AMD要等到32nm才用