PCDVD數位科技討論區 - 瀏覽單個文章 - 2006秋季處理器論壇:AMD Barcelona Quad Core K8L Architecture實物圖片曝光

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1.SSE MOV instructions can be performed in the floating-point "store" pipe
2.Two SSE operations can be executed and one SSE move per cycle
3.Support an unaligned load/execute mode, which can improve instruction packing and decoding efficiency
4.Advanced branch prediction. Doubled the return stack size, more branch history bits, and built in a 512-entry indirect branch predictor
5.32-byte instruction fetch. Increases efficiency by reducing split-fetch instruction cases
6.Sideband stack optimizer. Adjustments to the stack don't take up functional unit bandwidth.
7.Out-of-order load execution. Load instructions can actually bypass other loads in some cases, as well as stores that are not dependent on the load in question. This minimizes the effect of L2 cache latency.
8.Optimizations to the TLBs (translation lookaside buffers)
9.Additional Fastpath instructions
10.Extensions to bit manipulations and SSE instructions
11.Independent memory controllers, which enables more memory pages to remain open
12.Memory controllers now support full 48-bit hardware addressing, which theoretically allows for 256 terabytes of physical memory
13.Implemented 1GB memory page size in addition to the common 4KB and 2MB page sizes
14.L1 cache is 64KB, the L2 cache is 512KB dedicated per core and the L3 cache is 2MB shared between 4 cores to better suited for coming age of virtualization.
15.Improved hardware support for virtualization through virtualized address translation, instead of the current shadow paging.
16.Supports separate CPU core and memory controller power planes to allow CPU to lower its power state while the memory controller is running full bore
17.Enhanced AMD's PowerNow allows individual core frequencies to lower while other cores may be running full bore

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