總算有機會 qualify 別人, 而不一直當 followers.
註: Cadence 是美國公司專精於電子電路設計輔助系統(EDA).

剛剛在 Cadence 網站上看到的新聞:

Taiwan Semiconductor Manufacturing Company, Ltd. [(TSMC) (TAIEX: 2330, NYSE: TSM)], the world's largest semiconductor foundry, and Cadence Design Systems, Inc. (NYSE:CDN) today announced planned integration of Cadence® Encounter™ RTL Compiler into TSMC's next-generation Reference Flow. TSMC's qualification of Cadence's RTL Compiler marks another milestone in the companies' long-standing design chain collaboration.

The inclusion of RTL Compiler addresses key nanometer performance goals, improves timing closure, reduces device area and lowers power consumption for complex multi-million-gate system-on-chips (SoCs). RTL Compiler effectively uses TSMC's multiple-Vt (voltage threshold) libraries to optimize performance and leakage power in a single-pass optimization flow.

"We intend to instill designer confidence that high quality silicon is achievable, despite escalating chip complexity," said Genda Hu, vice president of corporate marketing at TSMC. "Integrating Cadence's RTL Compiler into our next-generation Reference Flow should help resolve challenging design issues and leverage TSMC libraries."

"As designers of complex industry leading graphics chips, we require the next-generation synthesis capabilities offered by Cadence's RTL Compiler," said Greg Buchner, vice president of engineering at ATI Technologies Inc. "By using RTL Compiler for some of our designs, we have been able to realize improved timing and reduced chip area along with a shortened design cycle time. The design methodology advances resulting from close collaboration between our partners TSMC and Cadence are important to our continuing success."



原文:http://www.cadence.com/company/news...&lid=press_area