PCDVD數位科技討論區 - [重要更新]3ware 9650SE/9690SA新版f/w發佈...

請各位務必更新..
另外早在前一版已正確支持2TB規格以上的HDD...
http://www.lsi.com/downloads/Public...4.10.00.007.zip

Readme.txt for Beta firmware for LSI 3ware 9650SE and 9690SA RAID controllers v1.2
February 2011
Firmware version 4.10.00.021
Includes changes from previous beta version 4.10.00.016, 4.10.00.019, and 4.10.00.020.

prom0006.img is for the 9650SE
prom0008.img is for the 9690SA

See LSI 3ware KB article 10058 http://kb.lsi.com/KnowledgebaseArticle10058.aspx for instructions on how to flash upgrade the controller.

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Summary of changes from 4.10.00.016 release (which are also included in this 4.10.00.021 release):

SCR 2196: Unexpected controller soft resets
Fixed an issue with regards to deferral of write and read commands to help eliminate unexpected soft resets.

SCR 2217: Incomplete unit after multiple power failures when a RAID 1 unit is initializing after a rebuild.
This issue is fixed in this firmware version.

SCR 819: Controller may assert when cache is disabled in a RAID5/RAID6 configuration under heavy I/O load.
This issue is fixed in this firmware version.

SCR 2214: Performance drops during SES polling.
Fixed the issue where performance drops when a Storage Enclosure Processor (SEP) takes up to 700-800 msec to respond to SES polling.

Summary of changes in 4.10.00.019 release (includes the release changes listed above):

SCR FIRM03219: Pchip reset interrupt not handled
SCR FIRM03220: Put parity segment to free state completely when deallocate unused parity segment

Summary of changes in 4.10.00.020 release (includes the release changes listed above):

SCR FIRM03221 Fix unexpected soft reset due to out of buffer condition

Summary of changes in this 4.10.00.021 release (includes the release changes listed above):

SCR 2257 Firmware reports 200TB drive for 500GB drive when exportJBOD is enabled.
This issue has been fixed in this firmware.

SCR 1896 DCB corruption, sector 5 getting changed or zeroed, resulting in inoperable array
Removed allocation of memory in Timer thread and moved the staging of the DCBs into statically allocated memory.