PCDVD數位科技討論區 - 2006秋季處理器論壇:AMD Barcelona Quad Core K8L Architecture實物圖片曝光

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2006秋季處理器論壇:AMD Barcelona Quad Core K8L Architecture實物圖片曝光

引用:

1.SSE MOV instructions can be performed in the floating-point "store" pipe
2.Two SSE operations can be executed and one SSE move per cycle
3.Support an unaligned load/execute mode, which can improve instruction packing and decoding efficiency
4.Advanced branch prediction. Doubled the return stack size, more branch history bits, and built in a 512-entry indirect branch predictor
5.32-byte instruction fetch. Increases efficiency by reducing split-fetch instruction cases
6.Sideband stack optimizer. Adjustments to the stack don't take up functional unit bandwidth.
7.Out-of-order load execution. Load instructions can actually bypass other loads in some cases, as well as stores that are not dependent on the load in question. This minimizes the effect of L2 cache latency.
8.Optimizations to the TLBs (translation lookaside buffers)
9.Additional Fastpath instructions
10.Extensions to bit manipulations and SSE instructions
11.Independent memory controllers, which enables more memory pages to remain open
12.Memory controllers now support full 48-bit hardware addressing, which theoretically allows for 256 terabytes of physical memory
13.Implemented 1GB memory page size in addition to the common 4KB and 2MB page sizes
14.L1 cache is 64KB, the L2 cache is 512KB dedicated per core and the L3 cache is 2MB shared between 4 cores to better suited for coming age of virtualization.
15.Improved hardware support for virtualization through virtualized address translation, instead of the current shadow paging.
16.Supports separate CPU core and memory controller power planes to allow CPU to lower its power state while the memory controller is running full bore
17.Enhanced AMD's PowerNow allows individual core frequencies to lower while other cores may be running full bore

Extremetech

補充一下！取自Extremetech中後段的重點！

Also new is an enhanced version of AMD's PowerNow. Previously, PowerNow would allow the CPU to reduce its frequency as needed, on a per-socket basis. Barcelona will allow individual core frequencies to lower while other cores may be running full bore. Note that voltages will not change on a per core basis, but lowering the frequency should still help with heat generation.

AMD estimates that the power consumption of a Barcelona will fit within a 95W envelope. An example cited for a two-socket system, plus memory, plus the chipset, is estimated at about 240W (not counting graphics and storage.)

意思好像是K8L四核心使用中！允許某些核心閒置時採用降頻方式來節能和降溫！而其他核心仍然可以以全速去執行程式！而且功耗是控制在95w的範圍以內！

重點是什麼時候才要推出呢????

引用:

作者ant1228

補充一下！取自Extremetech中後段的重點！

好像有看到我名字??

這是"碼"嗎?

引用:

作者vanness70087

重點是什麼時候才要推出呢????

伺服器版明年

桌上型2008(跟當年K8推出時一樣)....

引用:

作者ExtremeTech

好像有看到我名字??

這是"碼"嗎?

真幽默, 你沒眼花.......:laugh: :laugh: :laugh: