Sun's Niagara's RTL available to download (EE 好物 )
 

http://opensparc-t1.sunsource.net/download_hw.html

What you get (and what you need to use it):

This download area is for hardware design and verification engineers, it includes


Verilog RTL for OpenSPARC T1 design

Verification environment for OpenSPARC T1

Diagnostics tests for OpenSPARC T1

Scripts and Sun internal tools needed to simulate the design and to do synthesis of the design

Open source tools needed to simulate the design

System Requirements:


SPARC CPU based system with Solaris 9 or Solaris 10 Operating System

C/C++ Compiler, if you don't have it download Sun Studio 11.

Commercial EDA tools Requirements:


Verilog Simulator : Synopsys VCS or Cadence NC-Verilog

Synthesis : Synopsys Design Compiler



Nice annotated die photo of Niagara here btw:
http://opensparc.sunsource.net/imag...overlay_die.jpg

Pretty decent write-up about the event here:
http://www.itjungle.com/breaking/bn032106-story01.html

It notes that a start-up has been formed with the aim of bringing a single-core version out for the embedded market.


I came across this blog by David Miller, who's working on SPARC support in Linux. He has some interesting comments on Niagara (and other SPARC aspects):
http://vger.kernel.org/~davem/cgi-bin/blog.cgi


PS http://blogs.sun.com/roller/page/jo...is_the_computer
Sun's $1/CPU-hour utility grid is set to go live any day now. For US anyway (blame export restrictions), with other country specific sites going live later.

One thing they've been working on is to make the user interface really really simple. Looks like later on it'll be accessable as a web-service - ie you could get your own code to offload processing to Sun's grid in software.


懂得可以玩
不懂去上幾個課再來

完全不懂 有高手可以解說一下嘛

看起來像SUN(昇陽)公司出產的RISC CPU，
型號是UltraSPARC T1 的Soft IP釋放。
可供學術界模擬，驗證，以及開發相關的硬體設備，甚至是SOC系統。
小弟學藝不精，有不足處請糾正。 :ase

是SUN 最新的CPU 的完整 RTL Model
不是什麼老東西

h7878220: 您知道RTL (Register (level) Transfer Language) 是什麼嗎 ???

太正點了。
尤其那個crossbar switch。
加入本人的收集。
現在已有MIPS, ARM, DSP, SPARC等Verilog code

沒錯那個就是T1 的精華

就請大大用中文幫大家講解一下吧

對不起 :cry: 完全看不懂
我是機械科的啦 :D

你們元件製造畫 CAD 圖
像Pro-E

High level 設計IC 的畫這個