K10的L1、L2時脈都和Cache同步，L3才是自己的時脈 :)

我記得K10的設計是L1,L2跟CPU同步

L3則是跟HTT同步

如有記錯請鞭 :ase

嗯 Phenom這樣子還是很難令人興奮阿..

在第七頁
From the load and store buffers, memory operations proceed to access the cache hierarchy, which has been totally redone from top to bottom. As with the P4, both the caches and TLBs are dynamically shared between threads based upon observed behavior. Nehalem’s L1D cache has retained the same size and associativity (check) as the previous generation, but the latency increased from 3 to 4 cycles to accommodate timing constraints. As previously mentioned, each core can support more outstanding misses (up to 16) to take advantage of the extra memory bandwidth.
整篇英文太多了，就等對岸翻譯了。

CPU架構圖↓↓

Phenom X4 9950這顆CPU耗電量高達140W，會不會太誇張了 :stupefy: :stupefy: :stupefy:

等製程轉為 45nm 後，功耗應該會往下降。

或等 AMD 把 65nm 玩熟了，功耗也會降低。不過近來 Intel 製程升級的速度似乎加快了，AMD 恐怕沒機會玩熟 65nm，就被迫要盡快進入更先進製程，否則虧損會加劇 :stupefy:

這產品一點都不符合節能減碳.

http://www.amd.com/us-en/Processors...5e10272,00.html

大家好像都忘記AMD有Cool'n'Quiet :confused: :sleep: :jolin:
TDP 140W又不是一直140W在消耗......

跟intel比 還是比較耗電 :like: